The present invention relates generally to field-programmable gate arrays (FPGAs) and specifically to a FPGA that uses reconfigurable dynamic programmable logic arrays (DPLAs).
A PLA (programmable logic array) produces a predetermined set of outputs for a given set of inputs. Each output is a sum-of-products of a subset of the inputs, implemented using an AND plane to generate the product terms and an OR plane to generate the sums of the product terms. A dynamic PLA implements the sum-of-products functions by precharging and conditionally discharging wired-NOR circuits that are built within the AND and OR arrays. These functions are programmed when a dynamic PLA is built such that the array can only produce the same set of output signals for a given set of input signals. A dynamic PLA is xe2x80x9cprogrammablexe2x80x9d only in the sense that it is easy to implement desired functions within the array when the array is built but not in the sense that the array can be programmed to provide different functions once the array is built.
Dynamic programmable logic arrays (DPLAs) are utilized extensively. As shown in FIG. 1, a DPLA 5 includes input signals 2 to an AND plane 10 whose outputs 18 are then the inputs to an OR plane 14 that produces the output signals 20. The outputs of the AND plane 10 are known as AND term signals (A1 to Am). The outputs of the OR plane are known as OR term signals (O1 to On). FIG. 1 shows k number of inputs, m number of AND term signals, and n number of OR term signals. The AND plane 10 further comprises multiple NOR term generators 12, each of which outputs a wired-NOR signal 18 that is first precharged to Vcc (the supply voltage) and then conditionally discharged to GND (the ground voltage). The Vcc and GND can represent high (TRUE) and low (FALSE) logic states, respectively. Similarly, the OR plane 14 also comprises multiple NOR term generators 16, each of which outputs a wired-NOR signal 20 that is first charged to high logic level and then conditionally discharged to low logic level. For simplicity, the clocks that control the precharge and discharge are not shown in FIG. 1.
FIG. 2 shows two NOR term generators 12 in the AND plane. The wired-NOR signal 30 is discharged if one or more input signals 2 that are xe2x80x9cprogrammedxe2x80x9d to affect this output signal are high. An input signal 2 is programmed to affect an output signal by providing an evaluate circuitry 32 controlled by the input signal 2. FIG. 2 shows that the input signals I1 and I2 are programmed to affect the AND term signals A1 and A2. If the evaluate circuitry labeled 34 were not provided, for example, then the input signal I1 cannot affect the AND term signal A1 while it still affects the AND term signal A2.
FIG. 3 shows a conventional evaluate circuitry 38 for DPLA and the precharge transistor 40 and the discharge transistor 42 for the AND term signal. This precharge and conditional discharge circuitry is controlled in two non-overlapping phases, known as precharge and evaluate. During the precharge phase, both CLKP and CLKD are held low so that precharge transistor 40 is turned on and the discharge transistor 42 is turned off, forcing the output signal NL to be high. During the evaluate phase, both CLKP and CLKD are held high so that the precharge transistor 40 is turned off and the discharge transistor 42 is turned on. During the evaluate phase, if the input signal 46 is high to turn on the evaluate transistor 44, then the charge stored at the output signal NL is discharged via the transistors 44 and 42, resulting in the signal NL being low. If on the other hand, if the input signal 46 is low during the evaluate phase, the evaluate transistor 44 is turned off and the charge stored at the output signal NL remains high. The input signal 46 must not change during the evaluate phase to avoid falsely discharging the output signal NL.
A NOR term generator 12, which comprises one precharge transistor and one discharge transistor and at least one evaluate circuitry, works as follows. During the precharge phase, the precharge transistor 40 is turned on and the discharge transistor 42 is turned off, forcing the output signal NL to be high. During the evaluate phase, the precharge transistor 40 is turned off and the discharge transistor 42 is turned on. During the evaluate phase, if one or more input signals that are programmed to affect this output are high, the charge stored at the output signal NL is discharged and NL becomes low. If none of the input signals are high, then there is no path for the charge stored at NL to be discharged and the NL remains high. The NOR term generators 16 in the OR plane 14 works as same as those in the AND plane 10.
FIGS. 2 and 3 show a DPLA whose output node is precharged to Vcc by a p-transistor and conditionally discharged by two n-transistors in series connected to GND. Alternatively, an n-transistor precharged to GND and conditionally discharged by two p-transistors in series connected to Vcc can be used. Furthermore, the discharge transistor 42 may be omitted if the inputs are guaranteed to be zero or one, if the evaluate transistor is an n-transistor or a p-transistor, respectively, during precharge. Multiple dynamic PLAs can also be connected in a series, known as cascaded dynamic PLAs, such that one signal starts the evaluate phase of the PLAs in succession using self-timed logic.
A detailed description of DPLA can be found in xe2x80x9cPrinciples of C-MOS VLSI Designxe2x80x9d by N. H. Weste and K. Eshraghian, Addison-Wesley, 2nd Edition, 1993, Chapter 8, pages 595-602 or in the U.S. Pat. No. 4,769,562.
Dynamic PLA with Fine-Grained Control
The evaluate module 38 in FIG. 3 is replaced with the configurable evaluate module 80 in FIG. 4 in both the AND and OR planes to provide the complete control of the AND and OR term generators in the resulting PLA. That is, instead of using the evaluate module 38 only in the places where the input signals affect the AND term outputs and in the places where the AND term outputs affect the OR term outputs, a configurable evaluate module 80 is placed in everywhere so that every input signals can affect all AND term outputs and that every AND term output signal can affect all OR term outputs.
The configurable evaluate module 80 comprises an input pass transistor 54, an evaluate transistor 44, and an evaluate disable transistor 56. The control signal C enables either the input pass transistor 54 or the evaluate disable transistor 56 at any given time. When the input pass transistor 54 is turned on, the input signal 46 is allowed to affect the evaluate transistor 44, such that the evaluate transistor 44 is turned on or off if the input signal 46 is high or low, respectively. When the evaluate disable transistor 56 is turned on instead, the input signal 46 cannot affect the evaluate transistor 44.
This arrangement of configurable PLA results in a large number of control signals, since each conditional evaluate module 80 requires a dedicated control signal. For a PLA with K number of inputs, M number of AND terms, and N number of OR terms (or the outputs), a total of Kxc3x97M+Mxc3x97N=Mxc3x97(K+N) number of control signals. With such a large number of control signals for a PLA, a preferred method of generating these control signals would be to store the control signals in a memory array (SRAM, DRAM, flash, electrically programmable ROM, electrically erasable programmable ROM, fusible links, or even one-time programmable memory). In this way, the array can be configured to produce any desired function by reading the control signals from the memory array. To avoid falsely discharging the evaluate transistors, the control as well as the input signals must not change during the evaluate phase.
Dynamic PLA with Built-In Configurations
Building the configurations into the array can minimize the required number of control signals. A configurable evaluate module 100 in FIG. 5 can be used instead of the configurable evaluate module 80 in FIG. 4 in every place so that every input signals can affect all AND term outputs and that every AND term output signal can affect all OR term outputs. This arrangement reduces the required number of control signals to L, where L is the number of different configurations.
The configurable evaluate module 100 comprises an input control module 200, an input pass transistor 54, an evaluate transistor 44, and an evaluate disable transistor 56. The input control module 200 comprises a plurality of input control settings 202, a multiplexor 204 and the L-bit SEL signal that selects one of the L input control settings. To select the configuration j, the jth signal in SEL is asserted and all other signals in SEL are de-asserted to allow the jth configuration to affect the signal I. Each input control setting is hardwired to the low or high logic state, depending on whether the input signal 46 should or should not affect the evaluate transistor 44, respectively, when the setting is selected. The input signal 46 and the SEL signal should not change during the evaluate phase to avoid falsely discharging the NL output.
The output of the input control module 200 enables either the input pass transistor 54 or the evaluate disable transistor 56 at any given time. When the input pass transistor 54 is turned on, the input signal 46 is allowed to affect the evaluate transistor 44, such that the evaluate transistor 44 is turned on or off if the input signal 46 is high or low, respectively. When the evaluate disable transistor 56 is turned on instead, the input signal 46 cannot affect the evaluate transistor 44.
To simplify the generation of the SEL signal, it may be desirable to place configuration holding latch 208 that can be written only during the precharge phase, as shown in FIG. 6. The latch 208 allows the SEL signal to be changed in precharge and evaluate phases.
Dynamic PLA with Built-In Reprogrammable Configurations
An input control setting 202 can be made xe2x80x9creprogrammablexe2x80x9d by using a storage element, such as a latch 206 shown in FIG. 7, instead of hardwiring the setting to the low or high logic state.
FIG. 8 shows a configurable evaluate module in which all input control settings are made reprogrammable. To program all of the L input control latches 206 in one cycle, the desired values are placed on the L-bit PD signal and the PC signal is asserted (set to high and then to low). Each NOR term generator has a dedicated PC signal but shares the K number of L-bit PD signals with other generators in the AND plane so that all input control settings in the AND plane can be reprogrammed in M number of cycles, as shown in FIGS. 9 and 10. Similarly, each NOR term generator in the OR plane has a dedicated PC signal but shares the M number of L-bit PD signals so that all input control settings in the OR plane can be reprogrammed in N number of cycles. The connection of the SEL signal is not shown in these two figures. The PD, PC, input signal 46 and the SEL signals should not change during the evaluate phase to avoid falsely discharging the NL output.
All of the input control settings that are xe2x80x9creprogrammablexe2x80x9d can be connected in one scan chain to minimize the number of PD and PC signals, as shown in FIG. 11. In this arrangement, the input control settings are built using scan registers 210, shown in FIG. 12, and are connected as one scan chain. That is, the scan_in signal is connected to the program data input of the first scan register whose output is then connected to the program data input of the next scan register, and so forth. The output of the last scan register in the scan chain scan_out is then connected to the scan_in of first scan register in another configurable evaluate module 100, resulting in all of the scan registers in the logic planes being connected as one scan chain. The scan control signals sclk_a and sclk_b are connected to all scan registers in the same scan chain.
If only one configuration is needed, the multiplexor 204 and all but one of the storage element can be removed, leaving the evaluate module 100 reprogrammable but not configurable. The storage element can also use SRAM, flash memory, electrically programmable ROM, electrically erasable programmable ROM, or fusible links instead of a latch.
Dynamic PLA with Partitioned Configuration Control
A dynamic PLA with built-in hardwired or reprogrammable configurations can be partitioned into multiple sub-arrays with independent configuration controls by providing multiple SEL signals. For instance, the AND plane can be divided into four sub-arrays 301, 302, 303, and 304, as shown in FIG. 13. The SEL1 signal is connected to all configurable evaluate modules 310 in the sub-array 301. Similarly, the SEL2, SEL3, and SEL4 signals are used in the sub-arrays 302, 303, and 304, respectively. Note that the input signals I1 and I2 are connected to the two upper sub-arrays 301 and 302 while the input signals I3 and I4 are connected to the two lower sub-arrays 303 and 304. Similarly, the AND term generators A1 and A2 are connected to the two left sub-arrays 301 and 303 while the A3 and A4 are connected to the two right sub-arrays 302 and 304.
An AND term output is still affected by the settings of all of the configurable evaluate modules that are connected to it. For example, the A2 AND term output signal is affected by the settings of the configurable evaluate modules in both the sub-arrays 301 and 303.
A configurable array can be partitioned into different sized sub-arrays. The widths of the configuration select (SEL) signals can also be different, since the width of a SEL signal depends on the number of configurations used in the associated sub-array. If a sub-array uses only one configuration, then it obviously does not need a SEL signal.
Dynamic PLA with Partitioned Evaluate Control
The AND or OR plane of any dynamic PLA can be partitioned into multiple sub-arrays of varying sizes, each sub-array having a separate evaluate control clock. For example, FIG. 14 shows an array partitioned into three sub-arrays 401, 402 and 403, each array having a separate evaluate control clock CLKD1, CLKD2 and CLKD3, respectively. The advantage of this type of partition is that it is easy to control whether or not all of the evaluate modules in an sub-array affect the associated AND or OR term signals. That is, one evaluate control clock can override the inputs and the configuration settings for the associated sub-array so that all of the AND or OR term outputs that are connected to the sub-array are not affected by the sub-array. The same AND or OR term outputs can still be affected by other sub-arrays. For example, by not asserting the CLKD1 signal while asserting the CLKD3 signal during the evaluate phase, the inputs I1 and I2 are made to not affect the AND term A1 while I3 and I4 are allowed to affect A1.
Existing Programmable Semiconductor Devices
Programmable semiconductor devices are built using some combination of programmable logic structures and programmable interconnects. Programmable logic structures implement logic functions and programmable interconnects connect signals between the programmable logic structures. These devices can be programmed once and permanently or can be reprogrammed repeatedly. Many of these are known as FPGAs (field-programmable gate arrays) for their ability to be programmed xe2x80x9cin the fieldxe2x80x9d by end users. FIG. 15 shows a conceptual diagram of an existing FPGA, built using an array of CLBs (configurable logic blocks) surrounded by horizontal and vertical programmable interconnects. Each CLB consists of some amount of RAM, registers, multiplexors and a few combinational function units, which collectively can be programmed to generate any function of a small number of variables. Each input and output of a CLB can be programmed to connect to a predefined set of local interconnects, allowing most connections between adjacent CLBs to take place without using the horizontal and vertical interconnects. A programmable switching matrix is used at each junction of the horizontal and vertical interconnects, allowing desired connections between horizontal and vertical wires used for connecting signals between non-adjacent CLBs.
A detailed description of programmable CMOS devices can be found in xe2x80x9cPrinciples of CMOS VLSI Designxe2x80x9d by N. H. Weste and K. Eshraghian, Addison-Wesley, 2nd Edition, 1993, Chapter 6, pages 391-413.
Existing programmable semiconductor devices use static logic, as opposed to dynamic logic, in the programmable logic structures and interconnects, allowing any amount of logic structures and interconnects to be used within an arbitrarily long clock period simply by stretching the clock period. While requiring a simple clock control scheme, such devices are inadequate for implementing large, high-speed designs. What is needed is a better programmable semiconductor device that operates at a higher speed and requires a smaller area in implementing large, high-speed designs. The present invention addresses such a need.
Dynamic PLAs are used as the basis of constructing a new class of programmable devices called field-programmable dynamic logic arrays (FPDLAs). Unlike existing programmable devices that use static logic, the FPDLAs use reprogrammable and reconfigurable dynamic PLAs in programmable modules that provide both programmable logic and interconnect structures. A system of micro clocks is used to ensure that each dynamic PLA operates correctly by allowing it to start the evaluate phase after all of its inputs have become valid. Since dynamic PLAs with large numbers of inputs can be built in a small area, due to their regular circuit structure, and they produce the outputs in a time independent of the number of inputs affecting the outputs, FPDLAs can operate at a higher speed and require a smaller area than programmable devices built using static logic.